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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT195 4-bit parallel access shift register
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
4-bit parallel access shift register
FEATURES * Asynchronous master reset * J, K, (D) inputs to the first stage * Fully synchronous serial or parallel data transfer * Shift right and parallel load capability * Complement output from the last stage * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT195 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT195 performs serial, parallel, serial-to-parallel or parallel-to-serial data transfer at very high speeds. The "195" operates on two primary modes: shift right (QoQ1) and parallel load, which are controlled QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
74HC/HCT195
by the state of the parallel load enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is HIGH and shifted one bit in the direction Q0 Q1 Q2 Q3 following each LOW-to-HIGH clock transition. The J and K inputs provide the flexibility of the JK type input for special applications and by tying the pins together, the simple D-type input for general applications. The "195" appears as four common clocked D flip-flops when the PE input is LOW. After the LOW-to-HIGH clock transition, data on the parallel inputs (D0 to D3) is transferred to the respective Q0 to Q3 outputs. Shift left operation (Q3 Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input LOW. All parallel and serial data transfers are synchronous, occurring after each LOW-to-HIGH clock transition. There is no restriction on the activity of the J, K, Dn and PE inputs for logic operation other than the set-up and hold time requirements. A LOW on the asynchronous master reset (MR) input sets all Q outputs LOW, independent of any other input condition.
TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1,5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 15 57 3.5 105 HCT 15 57 3.5 105 ns MHz pF pF UNIT
December 1990
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Philips Semiconductors
Product specification
4-bit parallel access shift register
PIN DESCRIPTION PIN NO. 1 2 3 4, 5, 6, 7 8 9 10 11 15, 14, 13, 12 16 SYMBOL MR J K D0 to D3 GND PE CP Q3 Q0 to Q3 VCC NAME AND FUNCTION master reset input (active LOW) first stage J-input (active HIGH) first stage K-input (active LOW) parallel data inputs ground (0 V) parallel enable input (active LOW) clock input (LOW-to-HIGH edge-triggered) inverted output from the last stage parallel outputs positive supply voltage
74HC/HCT195
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
Fig.4 Functional diagram.
APPLICATIONS * Serial data transfer * Parallel data transfer * Serial-to-parallel data transfer * Parallel-to-serial data transfer FUNCTION TABLE INPUTS OPERATING MODES MR asynchronous reset shift, set first stage shift, reset first stage shift, toggle first stage shift, retain first stage parallel load Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition q, d = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW-to-HIGH clock transition X = don't care = LOW-to-HIGH clock transition L H H H H H CP X PE X h h h h l J X h l h l X K X h l l h X Dn X X X X X dn Q0 L H L q0 q0 d0 Q1 L q0 q0 q0 q0 d1 Q2 L q1 q1 q1 q1 d2 Q3 L q2 q2 q2 q2 d3 Q3 H q2 q2 q2 q2 d3 OUTPUTS
December 1990
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Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
Fig.5 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
4-bit parallel access shift register
74HC/HCT195
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 max. 190 38 33 190 38 33 95 19 16 100 20 17 100 20 17 100 20 17 125 25 21 100 20 17 3 3 3 5 24 28 120 24 20 120 24 20 120 24 20 150 30 26 120 24 20 3 3 3 4 20 24 -40 to +125 min. max. 225 45 38 225 45 38 110 22 19 ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 UNIT V WAVEFORMS CC (V) TEST CONDITIONS
min. typ. max. min. tPHL/ tPLH propagation delay CP to Qn propagation delay MR to Qn output transition time 50 18 14 41 15 12 19 7 6 80 16 14 80 16 14 80 16 14 100 20 17 80 16 14 3 3 3 6 30 35 17 6 5 11 4 3 17 6 5 33 12 10 25 9 7 -8 -3 -2 17 52 62 150 30 26 150 30 26 75 15 13
tPHL
ns
Fig.8
tTHL/ tTLH
ns
Fig.6
tW
clock pulse width HIGH or LOW master reset pulse width LOW removal time MR to CP set-up time J to CP set-up time K, PE, Dn to CP hold time J, K, PE, Dn to CP maximum clock pulse frequency
ns
Fig.6
tW
ns
Fig.8
trem
ns
Fig.8
tsu
ns
Figs 8 and 9
tsu
ns
Figs 8 and 9
th
ns
Figs 8 and 9
fmax
MHz
Fig.6
December 1990
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Philips Semiconductors
Product specification
4-bit parallel access shift register
DC CHARACTERISTICS FOR HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types
74HC/HCT195
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT PE all others
UNIT LOAD COEFFICIENT 0.65 0.35
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL tTHL/ tTLH tW tW trem tsu tsu th fmax propagation delay CP to Qn propagation delay MR to Qn output transition time clock pulse width HIGH or LOW master reset pulse width LOW removal time MR to CP set-up time J, K, PE to CP set-up time Dn to CP hold time J, K, PE, Dn to CP maximum clock pulse frequency 20 16 16 20 16 3 27 +25 typ. 18 17 7 6 6 6 12 6 -5 52 -40 to +85 -40 to +125 UNIT V WAVEFORMS CC (V) ns ns ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.8 Fig.6 Fig.6 Fig.8 Fig.8 Figs 8 and 9 Figs 8 and 9 Figs 8 and 9 Fig.6 TEST CONDITIONS
max. min. max. min. max. 32 35 15 25 20 20 25 20 3 22 40 44 19 30 24 24 30 24 3 18 48 53 22
December 1990
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Philips Semiconductors
Product specification
4-bit parallel access shift register
AC WAVEFORMS
74HC/HCT195
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V.
Fig.6
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency.
Fig.7
Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V.
Fig.8
Waveforms showing the data set-up and hold times for J, K and Dn inputs.
The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3V; VI = GND to 3 V.
Fig.9
Waveforms showing the set-up and hold times from the parallel enable input (PE) to the clock (CP).
December 1990
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Philips Semiconductors
Product specification
4-bit parallel access shift register
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
74HC/HCT195
December 1990
9

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